Programmable array logic (PAL) matrices utilize a semiconductor matrix having transistors arranged in rows and columns with fusible links between the emitter of the transistors and the bit line. The matrix has a programmable mode and an operating mode. In the programmable mode, it is necessary to select ones of the memory cells for programming by passing an increased level of current through the select memory cell to change the logic state. In order to select a memory cell, column and row decoders are provided on the chip for activation in the programming mode. In the operating mode, different inputs are utilized by multiplexing the pins to select predetermined rows and/or columns for combination with output logic circuitry to provide an output. This output is a function of the arrangement of memory cells and the logic state thereof that are interfaced with the particular output.
In the programming mode, it is necessary to receive the row and column addresses on predetermined pins for selecting a given row and column. The current through the select memory cell is then increased by raising the voltage on the associated output line that is interfaced with the associated column or bit line to break down an internal zener and increase the current through the select memory cell. This has a disadvantage in that the number of memory cells that can be programmed for a particular row and column address is determined by the number of output pins.
In a typical system, the memory cells are arranged in groups of programmed words such that one row from each group is associated with one output pin through associated output logic circuitry. In the operating mode, any number of word lines can be activated such that the memory cells associated therewith are interconnected with respective bit lines for interface with the output logic circuitry. However, in the programming mode, it is necessary to be able to select each memory cell for programming. To this end, a single word line is activated with the use of a row decoder and an associated input row address with a bit line selected from each group of memory cells for interface with the output pin. The output pin then has its voltage increased to break down the internal zener diode and supply additional current to the memory cell if the memory cell is to be opened. Therefore, with the use of the column decoder, the row decoder and the presence or absence of a high voltage on the output pin, each memory cell can be selectively programmed.
One of the primary disadvantages with prior art systems in the programming mode is that they require a predetermined number of pins for programming. In the operating mode, it may not be necessary to utilize this large number of pins to provide the desired logic function and, therefore, the additional pins would be required only for programming and would be useless after programming. For example, in a 32.times.64 having eight output pins, it is necessary to have five row decode pins for selecting one of thirty-two word lines and three column address lines for providing a three-bit column address for selecting among eight groups of the sixty-four bit lines with bit lines arranged in eight groups of eight-bit lines each. Each column address selects one bit line out of each of the eight groups for programming and the associated output pin provides an interface to the exterior of the package to allow the input of a programming voltage for each group. The programming voltage, of course, is required only if the fuse is to be opened. If it is to be closed, no program voltage is applied. A disadvantage to this system is that if more than 2048 memory cells are in the memory array, additional pins must be added in order to select and program the memory cells. Another disadvantage is the problem for emitter coupled logic circuits (ECL circuits) of raising the voltage of a selected output pin in selecting the cell for programming in a group of cells corresponding to that output pin. Typically, the latter voltage is about 10 volts and exceeds the breakdown voltage of ECL circuits. Therefore, there exists a need for improved techniques to select and program memory cells in a programmable memory matrix without raising the voltage on the output pins and without requiring additional pins.